The present invention relates to content addressable memory (CAM) cells. More specifically, the present invention relates to a space-efficient ternary CAM cell fabricated using standard ASIC or logic processes.
CAM cells are defined as memory cells that are addressed in response to their content, rather than by a physical address in an array. In a CAM cell array, a specified data string, or comparand, is compared to the data stored in each row of CAM cells. A match signal is generated by any row of CAM cells containing data that matches the comparand.
FIG. 1 shows a conventional CAM cell 100 as described in U.S. Pat. No. 4,833,643, issued May 23, 1989 to Hori. CAM cell 100 comprises a static random access memory (SRAM) cell 110, a match circuit 120, a word line WL, a bit line BL, a complementary bit line /BL, and a match line ML. SRAM cell 110 comprises NMOS access transistors 101 and 102, a data storage structure 103, and data storage nodes N1 and N2. Access transistor 101 is coupled between bit line BL and node N1, while access transistor 102 is coupled between node N2 and complementary bit line /BL. The gates of access transistors 101 and 102 are coupled to word line WL.
Match circuit 120 comprises NMOS transistors 121-124. Transistors 121 and 122 are serially coupled between match line ML and ground, thereby forming a stacked transistor string 125. Transistors 123 and 124 are likewise serially coupled between match line ML and ground, thereby forming a stacked transistor string 126. The gates of transistors 122 and 124 are connected to bit line BL and complementary bit line /BL, respectively. The gates of transistors 121 and 123 are coupled to data storage nodes N2 and N1, respectively.
During a read or write operation to CAM cell 100, word line WL is raised to a logic HIGH voltage, thereby turning on access transistors 101 and 102. Data on bit line BL and complementary bit line /BL is then written to data storage nodes N1 and N2, respectively, or data stored at nodes N1 and N2 can be read out to bit lines BL and /BL, respectively.
During a match operation, each bit of the input comparand is compared with a corresponding stored data bit in each row of CAM cells. At the start of the match operation, a data bit B, and a complementary data bit /B, are already stored at nodes N1 and N2, respectively, of SRAM cell 110. Word line WL is set to a logic LOW voltage and match line ML is precharged to a logic HIGH voltage. A comparand data bit C and its complementary data bit /C are applied to bit lines BL and /BL, respectively. If stored data bits B and /B do not match comparand data bits C and /C, respectively, both transistors in either transistor string 125 or 126 will be on and match line ML will be discharged to ground. If the stored data bits match the comparand data bits, CAM cell 100 does not provide a discharge path for match line ML. This match function performed on bits B and C by match circuit 120 is summarized in Table 1.
If any CAM cell in a particular row detects a no-match condition, the match line associated with that row is discharged. Therefore, a match for an input comparand is only indicated if every CAM cell in the row detects a match.
CAM cell 100 is a two-state, or xe2x80x9cbinary,xe2x80x9d device; i.e., the cell can store either a logic LOW or a logic HIGH. However, many modern CAM applications, such as Internet protocol (IP) and asynchronous transfer mode (ATM) communications networks, require a xe2x80x9cternaryxe2x80x9d storage capability. More specifically, the CAM cells in such applications must be able to store a xe2x80x9cDON""T CARExe2x80x9d state that returns a match signal regardless of the compare input. FIG. 2 shows a ternary CAM cell 200, as described in U.S. Pat. No. 5,319,590, issued Jun. 7, 1994 to Montoye.
CAM cell 200 provides ternary operation by combining two SRAM memory cells into a single circuit. CAM cell 200 comprises SRAM cells 210a and 210b bit lines BLa and BLb, complementary bit lines /BLa and /BLb, a word line WL, a match circuit 220, and a match line ML.
SRAM cells 210a and 210b are substantially similar to SRAM cell 110 of CAM cell 100 and operate in a similar fashion to store a data bit Ba and data bit Bb (provided via bit lines BLa and BLb, respectively) at data storage nodes N1a and N1b, respectively.
Match circuit 220 comprises NMOS transistors 221-224. Transistors 221 and 222 are serially coupled between match line ML and ground, forming a stacked transistor string 225. Transistors 223 and 224 are likewise serially coupled between match line ML and ground, forming a stacked transistor string 226. The gates of transistors 222 and 224 are connected to bit lines BLa and BLb, respectively. The gates of transistors 221 and 223 are coupled to nodes N1a and N1b, respectively.
During a write operation to CAM cell 200, word line WL is raised to a logic HIGH voltage, turning on access transistors 201a, 202a, 201b, and 202b. Data on bit lines BLa and BLb can then be written to data storage nodes N1a and N1b respectively. Complementary data can be written at the same time to data hold circuits 203a and 203b from complementary bit lines /BLa and /BLb, respectively. However, for the purposes of CAM cell 200, only the data stored at nodes N1a and N1b are relevant. SRAM cells 210a and 210b therefore operate as xe2x80x9chalf-cellsxe2x80x9d, wherein only half of the data stored within those cells is used for comparison purposes. Specifically, the complementary data within cells 210a and 210b are ignored.
During a typical write operation, a data bit B on bit line BLa and its complementary data bit /B on bit line BLb are stored at nodes N1a and N1b respectively.For example, to store a logic HIGH in CAM cell 200, a logic HIGH (bit B) is written to node N1a and a logic LOW (bit /B) is written to node N1b. Similarly, to store a logic LOW in CAM cell 200, a logic LOW (bit B) is written to node N1a and a logic HIGH (bit /B) is written to node N1b.
During a match operation, word line WL is set to a logic LOW voltage, turning off transistors 201a and 201b. Match line ML is precharged to a logic HIGH voltage, and a comparand data bit C and its complementary data bit /C are applied to bit lines BLb and BLa, respectively. If data bits B and /B are stored in CAM cell 200, XNOR match circuit 220 performs the comparison in much the same fashion as XNOR match circuit 120 shown in FIG. 1. If stored data bit B matches comparand data bit C, at least one transistor in each of transistor strings 225 and 226 will be turned off, and match line ML will be maintained at a logic HIGH voltage. If stored data bit B does not match comparand data bit C, both transistors in either transistor string 225 or 226 will be turned on, and match line ML will be discharged to ground.
In addition to the logic HIGH and LOW states described previously, CAM cell 200 can store a logic LOW value at both nodes N1a and N1b. This xe2x80x9cDON""T CARExe2x80x9d state causes CAM cell 200 to indicate a match condition for any comparand data bit C. Specifically, if a xe2x80x9cDON""T CARExe2x80x9d state is stored in CAM cell 200, match circuit 220 is turned off (i.e., transistors 221 and 223 are turned off, disabling stacked transistor strings 225 and 226, respectively), and match line ML will not be discharged regardless of the value of comparand bit C. These operations of CAM cell 200 are summarized in Table 2.
However, while CAM cell 200 does provide ternary operation, the increased functionality comes with a significant increase in overall cell size. The die area required for the SRAM cells is doubled over conventional binary CAM cells. The particular SRAM cells used in a ternary CAM cell therefore play a significant role in determining the overall size of the CAM cell.
Traditional static RAM (SRAM) uses either 4 transistors and 2 resistors (4T-2R) in each memory cell or 6 transistors (6T) in each memory cell as shown in FIGS. 3 and 4 respectively. The 4T-2R cell 300 shown in FIG. 3 includes NMOS access transistors 301 and 302, NMOS driver transistors 303-304 and load resistors 305 and 306. Load resistors 305 and 306 are typically polysilicon elements that require special processing, which is generally not available in a conventional ASIC or logic process.
The CMOS 6T cell 400 shown in FIG. 4 includes NMOS access transistors 401 and 402, NMOS driver transistors 403 and 404, and PMOS pull-up transistors 405 and 406. The large size of CMOS 6T cell 400, due to the use of both PMOS and NMOS transistors, limits the density of an array formed using these 6T cells.
To reduce the RAM cell size, resistors 305 and 306 of 4T-2R cell 300, or pull-up transistors 405 and 406 of 6T cell 400 can be eliminated to create the 4T RAM cell 500 shown in FIG. 5. 4T cell 500 includes NMOS access transistors 501 and 502 and NMOS driver transistors 503 and 504. An internal HIGH voltage level is stored on one of nodes N1 or N2 of cell 500, and an internal LOW voltage level is stored on the other one of nodes N1 or N2. The internal HIGH voltage level on node N1 or N2 of cell 500 can only reach the level of word line (WL) turn-on voltage applied to the gates of access transistors 501 and 502 minus one threshold voltage (VT). The internal HIGH voltage level can therefore be substantially lower than the Vcc supply voltage.
Because 4T RAM cell 500 is constructed with four transistors of the same polarity, significant leakage currents exist in cell 500. In a conventional ASIC or logic process, these leakage currents can include sub-threshold leakage, junction leakage and gate tunneling leakage currents. These leakage currents necessitate frequent refresh operations to restore the internal HIGH voltage level stored on node N1 or N2 of cell 500. Thus, cell 500 is a dynamic random access memory (DRAM) cell. Bias and refresh techniques which are used to prevent the complete loss of the internal HIGH voltage level are described in U.S. Pat. No. 3,949,383 entitled xe2x80x9cD.C. Stable Semiconductor Memory Cellxe2x80x9d by H. O. Askin et al., U.S. Pat. No. 4,023,149 entitled xe2x80x9cStatic Storage Technique For Four Transistor IGFET Memory Cellxe2x80x9d by A. R. Bormann et al., and U.S. Pat. No. 5,020,028 entitled xe2x80x9cFour Transistor Static RAM Cellxe2x80x9d by Frank Wanlass.
Moreover, while the internal HIGH voltage level on node N1 or N2 of cell 500 is being replenished, the leakage current through the other node (i.e., the LOW voltage node) can be several orders of magnitude higher than the normal leakage current, thereby resulting in very high standby current consumption.
In an attempt to overcome these problems, a larger 4T CMOS cell has been proposed by K. Takeda et al. in xe2x80x9cA 16 Mb 400 MHz Loadless CMOS Four-Transistor SRAM Macroxe2x80x9d, ISSCC 2000, pp. 264-265, Feb. 8, 2000. FIG. 6 illustrates this CMOS 4T cell 600, which includes PMOS access transistors 601 and 602 and NMOS driver transistors 603 and 604. The internal HIGH voltage level on node N1 or N2 of cell 600 is maintained through sub-threshold leakage current through access PMOS transistors 601 and 602, which is created by pre-charging bit lines BL and /BL to supply voltage Vcc.
Because an NMOS transistor is typically 3 times stronger than a PMOS transistor with the same drawn dimensions, CMOS 4T cell 600 can satisfy the cell stability requirements of standard SRAM read operations, which specify that the driver transistor should be 3 times the strength of the access transistor or more. This cell stability requirement is discussed in detail in U.S. Pat. No. 5,047,979 entitled xe2x80x9cHigh Density SRAM Circuit With Ratio Independent Memory Cellsxe2x80x9d by Wingyu Leung. One significant drawback of 4T CMOS cell 600 is that the gate tunneling current can be very high across the gate oxide of a turned-on NMOS transistor, particularly when the gate oxide has a thickness of 4 nm or less, as is the case in a conventional 0.18 micron ASIC or logic process. This high gate tunneling current exists due to very high electron density at either side or both sides of the thin gate dielectric. This high electron density will exist at the node (N1 or N2) that stores the internal HIGH voltage level, and is replenished by the low sub-threshold leakage current through the corresponding PMOS transistor.
Another drawback of 4T RAM cell 600 is that the sub-threshold leakage currents of PMOS transistors 603 and 604 decrease rapidly as the temperature decreases, while the tunneling current changes slowly as the temperature decreases, thereby making 4T RAM cell 600 unstable at lower temperatures.
Switching the NMOS and PMOS polarities can alleviate these problems somewhat. However, such a modification substantially increases the size of the cell since the PMOS driver transistors would then be required to be nine times the size of the NMOS access transistors to maintain SRAM read stability. Thus, conventional CAM cells, especially ternary CAM cells, are typically space/power inefficient.
Accordingly, it is desirable to provide a compact ternary CAM cell that is compatible with standard logic process.
The present invention provides a space-efficient ternary CAM cell that can be fabricated using a standard logic process, which is a single or twin well process with a single polycrystalline silicon layer and one or more layers of metal.
According to an embodiment of the invention, a CAM cell comprises two ratio-independent four-transistor (4T) SRAM cells. The two 4T SRAM cells enable the CAM cell to provide ternary functionality. Each of the 4T SRAM cells comprises a pair of cross-coupled driver transistors configured to store a data value, and a pair of access transistors coupled to the driver transistors. The driver transistors and access transistors are sized such that the driver transistors are less than three times stronger than the access transistors. In a particular embodiment, the driver transistors are not stronger than the access transistors. Because the driver transistors are not required to be stronger than the access transistors, the resulting 4T SRAM cells are ratio-independent memory cells.
In one embodiment, the driver transistors are PMOS transistors and the access transistors are NMOS transistors, with all of these transistors having substantially the same size. The PMOS and NMOS transistors are fabricated using a conventional ASIC or logic process, so the 4T SRAM cells can be easily incorporated into a system-on-a-chip (SOC) architecture. In one embodiment, the NMOS and PMOS transistors in the 4T SRAM cells are all fabricated with a channel length equal to the minimum channel length available with the process. As a result, the overall layout area of the CAM cell is advantageously minimized.
In one embodiment, each 4T SRAM cell comprises a first PMOS driver transistor coupled between the Vcc voltage supply terminal and a first data storage node (N1), a second PMOS driver transistor coupled between the Vcc voltage supply terminal and a second node (N2), a first NMOS access transistor coupled between the first node N1 and a bit line, and a second NMOS access transistor coupled between the second node N2 and a complementary bit line. The gates of all the NMOS access transistors are coupled to a word line. The second node in each 4T SRAM cell is connected to a match circuit, each match circuit comprising two PMOS transistors serially coupled between a xe2x80x9cmatch voltagexe2x80x9d and a match line.
According to a first aspect of the invention, the match circuits are controlled by data stored at the second node of each 4T SRAM cell and comparand data on compare lines. According to a second aspect of the invention, the match circuits are controlled by data stored at the second node of each 4T SRAM cell and comparand data on the bit lines, thereby eliminating the need for additional compare lines and improving layout efficiency.
The PMOS driver transistors can be located in an N-well coupled to receive a voltage greater than a Vcc supply voltage to decrease sub-threshold leakage and thus the standby current of the cell.
In an embodiment of the present invention, when the data stored at nodes N1 and N2 are not being accessed, the word and bit lines are held at a ground (i.e., logic LOW) voltage. This configuration allows the NMOS access transistors to provide enough leakage current to stably maintain the logic LOW node.
The bit lines can also be coupled to a differential regenerative sense amplifier. To read a data value from the CAM cell, the bit lines are isolated from any supply voltage terminal. A logic HIGH voltage is then asserted on the word line, thereby turning on the NMOS access transistors. At this time, a differential voltage representative of the data values stored at nodes N1 and N2 is developed on the bit lines. In response to the differential voltage across the bit lines, the differential regenerative sense amplifier pulls up one bit line to the Vcc supply voltage, and pulls down the other bit line to the ground potential. At the end of the read cycle, the word line is turned off before the sense amplifier is disabled. As a result, the sense amplifier causes the data value read from the CAM cell to be written back to the CAM cell.
During a match operation, the word line is set to a logic LOW voltage, thereby turning off the NMOS access transistors. The match line is then precharged to a predefined logic level, depending on the match voltage of the match circuits. According to a first aspect of the present invention, the match circuits are coupled between supply voltage Vcc and the match line, in which case the match line could be precharged to a logic LOW voltage. According to another aspect of the present invention, the match circuits could be coupled between supply voltage Vss (i.e., ground voltage), in which case the match line could be precharged to a logic HIGH voltage. Alternatively, with either form of match circuits, the match line could be allowed to float to begin the match operation.
A comparand data bit is then applied to one of the bit lines (associated with one of the 4T SRAM cells), and a complementary comparand data bit is applied to the other bit line (associated with the other 4T SRAM cell). If either of the match circuits detects a no-match condition within its associated 4T SRAM cell, then the match line is pulled to the match voltage of the match circuits. Otherwise, the match line remains at its precharge voltage, and a match condition is returned.
The present invention will be more fully understood in view of the following description and drawings.